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Silica Eda

MCP tools for RTL editing, simulation, synthesis, formal checks, FPGA implementation, programming, and serial testing.

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Install Silica Eda

Pick your client, then add it in one click or paste the config.

STDIOPython
~/Library/Application Support/Claude/claude_desktop_config.json
claude_desktop_config.json
{
  "mcpServers": {
    "silica-eda": {
      "command": "uvx",
      "args": [
        "silica-eda@latest"
      ]
    }
  }
}

Settings → Developer → Edit Config, merge this into mcpServers, then fully quit and reopen Claude Desktop.

Install not yet sandbox-tested— the server itself is confirmed live (we called its tools/list endpoint). The stdio install command is a separate, ongoing check.

Overview

silica-eda MCP server connects AI coding agents to locally installed HDL and FPGA tools through a standard MCP process launched with uvx. It provides structured results for linting, simulation, formal verification, synthesis, place-and-route, device programming, waveform analysis, coverage, and UART capture. Use it when an agent needs to inspect and modify RTL, run an iterative verification flow, or test a design on supported FPGA hardware. The doctor tool checks available EDA dependencies and reports fixes for missing or outdated tools.

Use cases

  • Inspect an unfamiliar RTL project and locate its source and constraint files
  • Run simulations, analyze failures, and inspect generated waveforms
  • Check RTL with lint, formal verification, equivalence, and coverage tools
  • Synthesize and place-and-route an FPGA design for timing and utilization results
  • Program a supported FPGA board and validate its UART output

Key features

  • Structured diagnostics for HDL simulation and linting
  • RTL editing, formatting, searching, and project inspection
  • Formal property checking and equivalence verification
  • Synthesis, FPGA place-and-route, and bitstream generation
  • Waveform and Verilator coverage analysis
  • FPGA programming and UART capture

Tools18

What Silica Eda lets your agent do. Expand a tool for its parameters.

Verified live~7.4k tokens of context

Security & health

What it can reach and how reliably it runs — from our own checks, not the maintainer’s claims.

ActiveLast checked 3d ago

Recent health check succeeded.

What it can do

From the 18 tools this server returned when we ran it.

Runs commands · 1Read-only tools · 17
Network at startup2 connections
Files written at startup21

Observed 2026-10-25 in an isolated sandbox. A description of reach, not a security audit.

Supply-chain signal

No high-severity advisories surfaced by our automated scan.

Critical 0High 0Medium 0Low 0

Scanned 7d ago via OSV.dev · silica-eda@latest (PyPI)

Adoption & maintenance

Factual signals from GitHub, npm, and our automated checks — not a rating.

GitHub stars12Stargazers on the source repository.
Last commit7d agoMost recent push to the default branch.
Tools exposed18Callable tools this server registers over MCP.

How Silica Eda works

What silica-eda does

silica-eda exposes an EDA workflow to MCP-compatible coding agents. Its tools can inspect a project, read and update RTL, search source files, review constraints, format SystemVerilog or Verilog, lint designs, simulate HDL, run cocotb tests, and perform formal property or equivalence checks.

The flow continues beyond verification. Synthesis returns utilization, timing information, inferred memories, and, for supported Yosys FPGA targets, a JSON netlist for implementation. Place-and-route consumes that netlist and reports timing, resource use, and the generated configuration file or bitstream. A separate programming tool loads supported bitstreams through openFPGALoader, while serial capture can check UART output from the running board.

Results are parsed into fields such as source locations, severities, failing endpoints, counterexample traces, coverage percentages, and memory mappings rather than exposing only tool logs.

How it works

The server runs external EDA programs installed by the user. Open-source dependencies are commonly supplied through OSS CAD Suite; commercial programs are used when available on PATH. The doctor tool identifies detected tools, versions, missing dependencies, and suggested fixes. It can also report the Python extras needed by cocotb and serial capture.

Project paths are generally confined to the project directory for source inspection and modification. A typical workflow starts with get_project_structure, then passes discovered RTL and constraint files to lint, simulation, synthesis, or place-and-route. Simulation can produce VCD traces and Verilator coverage data. Those artifacts can be inspected with read_waveform and read_coverage, or opened with a configured waveform viewer.

Formal verification accepts existing .sby, .eqy, or .tcl configurations, or generates configurations from source files and top-level information. An UNKNOWN proof with induction failures indicates that the induction step did not close; it is not reported as a reachable design failure.

Setup and configuration

Install uv, then configure an MCP client to launch:

bash
uvx silica-eda@latest

The repository documents setup for Claude Code, Claude Desktop, Codex CLI, Cursor, VS Code with GitHub Copilot, and Gemini CLI. Claude Code can also install the project plugin. The first uvx launch downloads the package into a cache, so clients configured this way need network access unless an offline installation workaround is used.

Install the EDA tools separately. OSS CAD Suite covers many open-source tools, while Verible, svlint, openXC7, and commercial tools may require separate installation. Run doctor after setup to check the environment. Set SILICA_NO_UPDATE_CHECK=1 to disable the optional PyPI update check.

Tools and capabilities

  • Inspect RTL, constraints, and project structure with get_project_structure, read_rtl, search_rtl, and get_constraints.
  • Review or commit source changes through dry-run diffs from write_rtl and format_rtl.
  • Lint multi-file Verilog and SystemVerilog designs with Verible, Verilator, svlint, or SpyGlass adapters.
  • Run Verilog, SystemVerilog, VHDL, and cocotb simulations with supported simulators, including Icarus, Verilator, GHDL, VCS, Questa, and Xcelium.
  • Collect waveform traces and Verilator line or toggle coverage, then inspect them as structured data.
  • Run property checking with SymbiYosys, JasperGold, or VC Formal, and RTL equivalence with eqy.
  • Synthesize for generic, FPGA, or selected commercial targets and inspect timing, utilization, and inferred memory details.
  • Place and route supported iCE40, ECP5, Nexus, MachXO2, and Xilinx architectures with nextpnr.
  • Program FPGA SRAM or SPI flash with openFPGALoader and capture explicitly selected UART ports.

Limitations and notes

Vivado is supported for synthesis only; it does not provide an implementation or bitstream stage through this server. Adapters for VCS, Questa, Xcelium, Quartus, DC Shell, JasperGold, VC Formal, SpyGlass, and Verdi have been tested with mocked calls rather than real installations. iCE40 and ECP5 packing is covered, but physical-board programming with openFPGALoader has not been validated on those board families.

Cocotb depends on compatibility between the Python glibc and the simulator being loaded. Deep bounded formal checks can take substantial time. capture_serial requires an explicitly supplied port with access permissions, and a boot message may occur before capture begins. Project structure discovery does not list iCE40 .pcf files. Windows has limited serial pre-check and pseudo-terminal test coverage.

Read the full README View source on GitHub

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Frequently Asked Questions about Silica Eda

silica-eda is an MCP server that connects AI coding agents to locally installed HDL and FPGA tools. Its main tools lint, simulate, synthesize, formally verify, place and route, program supported boards, inspect waveforms and coverage, and capture UART output, returning structured diagnostics and implementation results through MCP.

Install `uv`, then configure your MCP client to launch `uvx silica-eda@latest`. Install the required EDA tools separately, such as OSS CAD Suite or other documented tools, and run `doctor` after connecting to check what is available.

Yes, silica-eda works with Cursor through a standard stdio MCP configuration. Add a server entry using `uvx` as the command and `silica-eda@latest` as its argument in the user or project `mcp.json` file.

silica-eda supports Yosys-based synthesis targets and nextpnr place-and-route for iCE40, ECP5, Nexus, MachXO2, and Xilinx architectures. It can pack supported outputs when the relevant tools are installed, and uses openFPGALoader for device programming.

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